The Cybersecurity Group conducts research into cryptography and the hardware and software needed to implement secure systems. The group has particular interest in techniques practical cryptography, the efficient implementation of cryptography on small computing devices and the verification that such implementations do what they say they do.
Further information about the group is available also on www.cybersecurityresearch.at
RampUp Cybersecurity:
Doktorandlnnen für die Professur >Systemsicherheit<
Projektleitung: Univ. Prof. Dr. DI Elisabeth Oswald
Laufzeit: 13.05.2019 – 31.12.2022
Förderung: EFRE & KWF (Kärntner Wirtschaftsföderungs Fonds)
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Cybersecurity is a fundamental enabling technology that underpins all aspects of our (digital) livers ranging from personal privacy over business transactions to digital democracy. This newly established research group will work across different areas of cybersecurity bringing in specific expertise grounded in applied cryptography but drawing also on machine learning techniques.
Focus is laid on the advanced statistical estimation techniques for mutual information (Ml) in the context of side channel analysis. Furthermore areas of research are those of Deep Learning (DL). DL implementations are expected to be deployed in a range of devices, including embedded devices. Consequently, the implementation security becomes relevant.
Ultimately, research is done within the algebraic aspects of cryptography. From an algebraic point of view any cryptographic construction can be modeled as polynomial system. To implement modern protocols like multi-party computation efficiently many ciphers have been proposed that admit a very simple polynomial model. For these kind of ciphers algebraic attacks often are most performative. Consequently, an algebraic study of these primitives is relevant for their deployment.
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Dieses Projekt wird aus Mitteln des EFRE Europäischen Fonds für regionale Entwicklung kofinanziert. Nähere Informationen zu IWB/EFRE finden Sie auf www.efre.gv.at.
Sound and Early Assessment of Leakage for Embedded Software
Side channel attacks use, alongside information such as plaintexts or ciphertexts, leakage about the (secret) keydependent intermediate state(s), and deliver a `key ranking' as a result. Kocher's attacks showed, that formany practical implementations, observing a few encryptions made complete key recovery possible in practice. The academic research into combating these attacks so far has largely focused on approaches and tools to equip specialisedcryptographic engineers with access to a specialist lab and tools. The research hypothesis of this CoG is that one can make meaningful statements about the leakage behaviour ofarbitrary implementations on small devices by utilising a-priori derived (instruction level) leakage models. Our visionis to enable developers with limited domain-specific knowledge to perform side channel evaluations at design timewithout access to a fully equipped lab, by creating tools and methodologies that integrate a priori derived instructionlevel leakage models into a standard compiler.This vision is articulated in three overarching research objectives:1. Designing novel profiling strategies including novel leakage acquisition techniques to generate leakagemodels for a specific target device.2. Developing fast and comprehensive methods to support rapid evaluations (WP2).3. Integration of semantics, syntax and tools capable of using profiling information into a standard compilerwith the aim to evaluate and improve the side channel resilience of the target code. Addressing these goals simultaneously is required to make substantial progress towards the overall vision of thisproject. As a final result, we will make demonstrators available: using a off-the shelf components, we supply thenecessary tools and compiler enhancements including samples of cryptographic implementations to conduct analysesand demonstrate improvements regarding side channel resilience.
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Robust and Efficient Approaches to Evaluate Side Channel Resilience
Implementing cryptography on embedded devices is an ongoing challenge: every year new implementation flaws are discovered and new attack paths are being used by real life adversaries. Whilst cryptography can guarantee many security properties, it crucially depends on the ability to keep the used keys secret even in face of determined adversaries.Over the last two decades a new type of adversary has emerged, able to obtain, from the cryptographic implementation, side channel leakage such as recording of response times, power or EM signals, etc. To account for such adversaries, sophisticated security certification and evaluation methods (Common Criteria, EMVCo, FIPS…) have been established to give users assurance that security claims have withstood independent evaluation and testing.Recently the reliability of these evaluations has come into the spotlight: the Taiwanese citizen card proved to be insecure, and Snowden’s revelations about NSA's tampering with FIPS standards eroded public confidence.REASSURE will improve the efficiency and quality of all aspects of certification using a novel, structured detectmap-exploit approach that will also improve the comparability of independently conducted evaluations, cater for emerging areas such as the IoT by automating leakage assessment practices in order to allow resistance assessment without immediate access to a testing lab, deliver tools to stakeholders, such as reference data sets and an opensource leakage simulator based on instruction-level profiles for a processor relevant for the IoT, improve existing standards by actively pushing the novel results to standardization bodies.REASSURE's consortium is ideal to tackle such ambitious tasks. It features two major circuits manufacturers (NXP, MORPHO), a highly respected side channel testing lab (Riscure), an engaged governmental representative (ANSSI), and two of the most prominent research institutions in this field (UCL, University of Bristol).
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